Release 1.1Beta includes the following updates:

gen_vhdl updates:
- signals in data path implemented
- scheduling bugs fixes

Sim and Runtime Library updates:
- ported to Annapolis Micro Systems host API 5.0

VHDL hardware library updates:
- implemented block ram component, SC_Bram.  See the block ram section
	in the hardware library manual about how to write your own
	pragma to use the block ram in hardware processes.  There is
	not yet a software interface to the block ram.
- 32 bit external memory component, SC_Mem4
- minor bug fixes for strmfifo.vhd and signals.vhd components
- hardware library manual released

Limitations of Release 1.1Beta:
- the _arch.vhd file is not correctly generating signals and
	memory accesses
- arrays of processes are not implemented in the synthesis
	compiler
- parameters are not implemented in the synthesis compiler
- the block ram and memory types available are listed in
	the apps/arch/Firebird.def, not all documented types
	are currently available

Software Requirements for 1.1Beta:
- Red Hat Linux 6.2
- SUIF version 1.3.0.5
- Annapolis Micro Systems Firebird API 5.0.0
 
Hardware Requirements for 1.1Beta:
- PC with attached Annapolis Micro Systems
	Firebird board, running PCI version 2.8.0

Tools Required for VHDL simulation, compiling VHDL and 
	generating a bitstream (see doc/hw_lib hardware library manual 
	for more information):
- Modelsim PE 5.5e
- Xilinx Core Gen 3.3.07i
- Xilinx 4.1 Tools
- Synlify 7.0
- Annapolis VHDL version 3.1

Note: If you own a licence for Xilinx contact the authors to receive the
sc2 xilinx core components libraries.