-------------------------------------------------------------------------- -------------------------------------------------------------------------- Release 1.4Beta includes the following updates: synthesis compiler updates: -fixed signed arithmetic. In previous releases, signed arithmetic was not compiled correctly: all arithmetic operations were performed in unsigned mode. This problem has been corrected. -improved implementation of large constants. Constants larger than 2^32 are now printed in hexadecimal in the generated VHDL. Previously they were printed in decimal, and were not accepted by backend tools as the integer data type (which decimal format implies) is restricted to 32 bits. -implemented arrays of processes with bram memories and signals. -implemented connecting ports in a range of processes. -all memory types are available in /apps/arch/Firebird.def, Sim and Runtime Library updates: -added ability to use SystemC for fixed precision types, which allow for all but 128 bits for the sc integer widths in software processes and software simulation of hardware processes. -added sc_catenate(), sc_ror(), sc_rol() and sc_mod() intrinsics when using SystemC. -added sc_bit_insert() and sc_bit_extract() for 64 bit types (when not using the A|RT or SystemC libraries) on 32 bit or 64 bit machines. -increased signal and stream data width to 64 bits. -added .streamscrc_bash for bash users -update sc2 reference manual Testing highlights: -added streamssc/apps/array_bram -added streamssc/apps/array_sig -added streamssc/apps/array_range -added streamssc/apps/DES -added streamssc/apps/mult1 -added streamssc/apps/mult2 -added streamssc/apps/sigstrm64 VHDL hardware library updates: - updated hardware library modules for compatibility with the IEEE numeric standard package - added module for dual port ram, dpram.vhd - updated sc2 hardware library reference manual Limitations of Release 1.4Beta: - Direct Memory Access (DMA) is not implemented. - When using the unroll pragma, large unroll factors combined with large loop body may cause scheduling phase to run out of memory. - Frequent stalling will sometimes generate an error in unpipelined loops. We recommend use of external memory for inputting data from a software process to hardware process (especially when using nested loops) in order to minimize stalling and improve the timing efficiency of the routed design. - Definite loops are implemented as indefinite loops in the hardware synthesis compiler. Use of multiple external memories within a pipelined loop can cause a dead-lock stall condition due to design constraints in the indefinite hardware controller module. - For the hardware synthesis compiler, constant numbers (e.g. 100000) must be explicitly cast for use in bit intrinsic functions, defines, assignments, or in expressions otherwise their default type will be signed int. - Hardware defines for constants must be sc data types or they must be explicitly cast in each instance they are used. - See the hardware library reference manual for further issues and limitations. Software Requirements for 1.4Beta - Red Hat Linux 6.2 and above - SUIF version 1.3.0.5 - Annapolis Micro Systems Firebird API 5.0.0 Hardware Requirements for 1.4Beta - PC with attached Annapolis Micro Systems Firebird board (pn# 12676-0000 Rev A), running PCI version 2.8.0 Tools Required for VHDL simulation, compiling VHDL and generating a bitstream (see doc/hw_lib hardware library manual for more information): - Modelsim PE 5.5e - Xilinx Core Gen 4.1.03i - Xilinx 5.2 Tools - Synlify 7.1.1 - Annapolis VHDL version 3.2 (VHDL version that comes with the Annapolis API 5.0 software) -------------------------------------------------------------------------- -------------------------------------------------------------------------- Release 1.3Beta includes the following updates: synthesis compiler updates: - implemented hw-hw signals - arrays of processes are implemented - Optimization for external memory read implemented - scheduling bugs fixes - updated sc2 reference manual - source updated to compile under Redhat 8.0 - streamsc/apps/arch/Firebird.def file allows definition of all memory types - external memory, block ram, dualport block ram, and CLB ram Sim and Runtime Library updates: - changed end-of-stream sequence - added debug flag for synthesis - source updated to compile under Redhat 8.0 Testing highlights: - changed end-of-stream sequence - expanded stream fifo width for all sc2 data types and - expanded stream fifo depths to 16, 32 and 64 - bug fixes for unpipelined loops - added external memory optimizaton for memory read - added streamsc/apps/array - added streamsc/apps/fastfold - added streamsc/apps/mem3 SUIF Updates - suif 1.3.0.5 updated to compile under Redhat 8.0 VHDL hardware library updates: - all hardware library modules were updated for memory read optimzation and stream fifo width and depth expansion. - added fifo32.vhd and fifo64.vhd modules - hw-to-hw streams can have data widths of any sc2 data type while hw-to-sw streams must be 32-bits or less - new Xilinx cores for fifo components (available upon request) - added modules for rotate right, rotate left and modulus in strmshift.vhd - For Streams-C examples: strm1, strm2 - host_arch.vhd and system_cfg.vhd files for VHDL simulation available in apps/strm1/sim and apps/strm2/sim - updated sc2 hardware library reference manual Limitations of Release 1.3Beta: - do not use external memories with arrays of processes. Local memory allocation for arrays of processes is not yet implemented in the _arch.vhd file. See the sc2 Hardware Library Reference Manual for details. - all memory types are available in /apps/arch/Firebird.def, dual port ram types are not fully implemented in the _arch.vhd. - Direct Memory Access (DMA) is not implemented. - Unpipelined loops have not been exhaustively tested. - Streams and signals greater than 32 bits are not implemented correctly in the synthesis compiler. - When using the unroll pragma, large unroll factors combined with large loop body may cause scheduling phase to run out of memory. - Streams-C programs must have the CONNECT directive for streams and signals specified "source" to "destination" (i.e."producer" to "consumer"). - streamsc/apps/arch/Firebird.def file must have > 1, for number of blockram and dual port ram types. (i.e statement => 1 BLOCK_RAM1 Memory B_A_ size 128 allcates 1 block ram of type B_A_, named B_A_ The name, B_A_, causes a syntax error in the generated _all.vhd file.) Software Requirements for 1.3Beta - Red Hat Linux 6.2 and above - SUIF version 1.3.0.5 - Annapolis Micro Systems Firebird API 5.0.0 Hardware Requirements for 1.3Beta - PC with attached Annapolis Micro Systems Firebird board (pn# 12676-0000 Rev A), running PCI version 2.8.0 Tools Required for VHDL simulation, compiling VHDL and generating a bitstream (see doc/hw_lib hardware library manual for more information): - Modelsim PE 5.5e - updated to Xilinx Core Gen 4.1.03i - Xilinx 4.1 Tools - Synlify 7.0 - Annapolis VHDL version 3.2 (VHDL version that comes with the Annapolis API 5.0 software) -------------------------------------------------------------------------- -------------------------------------------------------------------------- Release 1.2Beta includes the following updates: gen_vhdl updates: - implemented signals, external memory and single ported block ram in top level (_arch.vhd file) - parameters and hw inititates in data path are implemented - scheduling bugs fixes - updated sc2 reference manual Sim and Runtime Library updates: - implemented hardware initiates and dual ported block ram access Applications testing highlights: - tested casting, explicit and implicit implemented correctly. - multiplication with sc2 data types, signed and unsigned implemented correctly. - unroll definite loops - unroll for entire length of loop - nested loops - only inner-most loop can be pipelined - multiple streams, multiple signals implemented correctly. - tested hw-to-hw signals. - single port blockram, all external memories implemented correctly. - release of frequently asked questions available in streamsc/FAQ - release of a suif installation script, streamsc/install_suif VHDL hardware library updates: - block ram VHDL module, bram.vhd - added logic for Stall on a read and registered output data - memory VHDL module, mem.vhd - burst writes for external memory - indefinite VHDL module, indefinite.vhd - check for flush = 0 after terminate - minor bug fixes for strmshift.vhd - created a sc_init VHDL component in signals.vhd for hardware inititates. - For Streams-C examples: ppf, kmeans, mem2 - host_arch.vhd and system_cfg.vhd files for VHDL simulation available in apps/app_name/sim - updated hardware library reference manual Limitations of Release 1.2Beta: - hw-to-hw signals and dual ported block ram are not implemented correctly in the synthesis compiler. - arrays of processes are not implemented in the synthesis compiler - all memory types are available in /apps/arch/Firebird.def, dual port ram types are not fully implemented. (Types commented out with a '#' are not implemented in the synthesis compiler yet.) Software Requirements for 1.2Beta have not changed (see below). Hardware Requirements for 1.2Beta have not changed (see below). Tools Required for VHDL simulation, compiling VHDL and generating a bitstream (see doc/hw_lib hardware library manual for more information): - updated to Annapolis VHDL version 3.2 (VHDL version that comes with the Annapolis API 5.0 CD) -------------------------------------------------------------------------- -------------------------------------------------------------------------- Release 1.1Beta includes the following updates: gen_vhdl updates: - signals in data path implemented - scheduling bugs fixes Sim and Runtime Library updates: - ported to Annapolis Micro Systems host API 5.0 VHDL hardware library updates: - implemented block ram component, SC_Bram. See the block ram section in the hardware library manual about how to write your own pragma to use the block ram in hardware processes. There is not yet a software interface to the block ram. - 32 bit external memory component, SC_Mem4 - minor bug fixes for strmfifo.vhd and signals.vhd components - hardware library manual released Limitations of Release 1.1Beta: - the _arch.vhd file is not correctly generating signals and memory accesses - arrays of processes are not implemented in the synthesis compiler - parameters are not implemented in the synthesis compiler - the block ram and memory types available are listed in the apps/arch/Firebird.def, not all documented types are currently available Software Requirements for 1.1Beta: - Red Hat Linux 6.2 - SUIF version 1.3.0.5 - Annapolis Micro Systems Firebird API 5.0.0 Hardware Requirements for 1.1Beta: - PC with attached Annapolis Micro Systems Firebird board, running PCI version 2.8.0 Tools Required for VHDL simulation, compiling VHDL and generating a bitstream (see doc/hw_lib hardware library manual for more information): - Modelsim PE 5.5e - Xilinx Core Gen 3.3.07i - Xilinx 4.1 Tools - Synlify 7.0 - Annapolis VHDL version 3.1 Note: If you own a licence for Xilinx contact the authors to receive the sc2 xilinx core components libraries.